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78P7200L E3/DS3/STS-1 Transceiver
Advanced Information
June 2000
DESCRIPTION The 78P7200L is a line interface transceiver IC for E3, DS3, STS-1, North America T3 and ATM applications. It includes clock recovery and transmitter pulse shaping functions for applications using 75-ohm coaxial cable at distances up to 1100 feet. These applications include DSLAMs, T3/E3 digital multiplexers, SONET Add/Drop multiplexers, PDH equipment, DS3 to Fiber optic and microwave modems and ATM WAN access for routers and switches. The receiver recovers clock and positive data and negative data from an AMI signal. It can compensate for over 12dB of cable and 6dB of flat loss. The transmitter generates a signal that meets the standard pulse shape requirements. The 78P7200L is pin and functionally compatible to the 78P7200. It adds loop-back and clock polarity selection. The 78P7200L is manufactured in an advanced BICMOS process and operates at both 5V and 3.3 V power supply voltages. It consumes less than 95 mA of supply current.
FEATURES * * * * * * * * * * * * Single chip transmit and receive interface for E3, DS3 and STS-1 applications. Interface to 75 ohm coaxial cable over 1100 feet at speeds up to 51.84 Mbps. Compliant with ANSI T1.102-1993, Telcordia GR-499-CORE and GR-253-CORE, ITU-T G.703 and G.823 for jitter tolerance. Compliant with ATM FORUM af-phy-0034 (E3 public UNI) and af-phy-0054 (DS3 public UNI). Easily Interfaced to ATM framer ICs such as PMC 7345 , 7346 QJET and 7321. Unique clock recovery requires no reference clock or crystal oscillator. Receive DS3-high signal Includes diagnostic loop-back for AMI and digital signals. Pin compatible to 78P7200 and 78P2241 (28lead PLCC). 28-lead PLCC and 48-lead TQFP packages 3.3 or 5 V operation, ICC<95mA Input circuit works either Transformer or Capacitor coupled
BLOCK DIAGRAM
TXEN LPBK LBO
TPOS TNEG TCLK
Binary to AMI
PULSE SHAPER
LOUTP LOUTN
RPOS RNEG
AMI to Binary
Data Slicer
Adaptive Equalizer Clock Recovery
LINP LINN
RCLK
Biasing
Signal Detector
LPBK
RFO
LOS
LF
78P7200L E3/DS3/STS-1 Transceiver
FUNCTIONAL DESCRIPTION
The 78P7200L is a single chip line interface IC designed to work with a 51.84 Mbit/s STS-1, 44.736 Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver recovers clock, positive data and negative data from an Alternate Mark Inversion (AMI) signal. The AMI line input signal should be B3ZS or HDB3 coded. The transmitter accepts clock, positive, and negative data and converts them into an AMI signal to drive a 75 coaxial cable. The shape of the transmitted signal though any cable length of 0 to 450 feet complies with the published templates of ANSI T1.102-1993, Telcordia TR-NWT-000499 and GR-253-CORE, ITU-T G.703. The 78P7200L is designed to work with B3ZS or HDB3 coded signals. The B3ZS or HDB3 encoding and decoding functions can be included in the framer ICs. The 78P7200L is designed to easily connect to popular ATM framer ICs such as PMC 7345 (SUNIPDH), PMC 7346 (QJET) and 7321. OPERATION SPEED Internal bias generators that are adjusted by the value of the RFO set the 78P7200L PLL center frequency and Transmitter amplitude for the different standards. The E# pin controls the equalizer response and the transmitter pulse shape and amplitude. The following table shows the proper settings. STANDARD E3 DS3 STS-1 RFO VALUE, K 6.81 5.23 4.53 E# PIN SETTING Low High Float RECEIVER The receiver input can be either transformer-coupled or capacitor coupled to the AMI signal. In applications where the highest performance and isolation is required, a 1:1 transformer is used on the receiver path. In the applications, where isolation is provided elsewhere in the circuit, an AC coupling can be used. The inputs to the IC are internally referenced to Vcc. Since the input impedance of the 78P7200L is high, the AMI line must be terminated to 75. The input signal of the 78P7200L must be limited to a maximum of three consecutive zeros using a coding scheme such as B3ZS or HDB3. The AMI signal first enters an equalizer and AGC gain stage. The equalizer is designed to overcome intersymbol interference caused by long cables. Because the equalizer is adaptive, the circuit will work with all square shaped signals such as DS3 high or 34 Mbit/s E3. The variable gain differential amplifier maintains a constant voltage level output regardless of the input voltage level. The gain of the amplifier is adjusted by detecting the peak of the signal and comparing it to a fixed reference. Outputs of the data comparators are connected to the clock recovery circuits. The clock recovery system employs a phase locked loop with an auxiliary frequency-sensitive acquisition loop. This system permits the loop to independently lock to the frequency and phase of the incoming data stream without the need for an external, high precision tuned circuits or reference clock signal. The jitter tolerance of the 78P7200L meets the requirements of Telcordia GR-499-CORE for Category I equipment for DS3 rates and exceeds the requirements of ITU-T G.823 for E3 rates.
2
78P7200L E3/DS3/STS-1 Transceiver
FUNCTIONAL DESCRIPTION (continued) LOSS OF SIGNAL Should the input signal fall below a minimum value, the loss of signal indication, LOS goes low. TRANSMITTER The transmitter accepts logic level clock (TCLK), positive data (TPOS) and negative data (TNEG) signals and generates current pulses on the LOUT+ and LOUT- pins. When properly connected to a center-tapped 1:2 transformer, an AMI pulse is generated which can drive a 75 coaxial cable. When the recommended transformer is used and the E# pin is set high, the transmitted pulse shape at the end of the 75 terminated cable of 0 to 450 feet will fit the DS3 template in ANSI T1.102-1993 and Telcordia GR-499-CORE standard documents. For STS-1 applications, the transmitted pulse for a short cable meets the requirements of TelcordiaGR253-CORE. The E# pin should be allowed to float. For E3 applications, the transmitted pulse for a short cable meets the requirements of ITU-T G.703. The E# pin is to be pulled low. RCLK/TCLK POLARITY REVERSAL: To simplify the interface with framer circuitry, RCLK and TCLK can be inverted with the ICKP pin. PIN 10 ICKP Low Float High Normal Invert Normal Normal Invert Invert RCLK TCLK LOOP-BACK MODES: The following loop-back modes allow for the diagnostic test of the PC board. This function is controlled by the LPBK pin.
PIN 40/TQFP PIN 28/PLCC LPBK Low Float High
LOOP-BACK
Local loop-back (LLB) Remote loop-back (RLB) Normal Operation
LOCAL LOOP-BACK: When LPBK is low, the 78P7200L enters Local loopback. In this mode, the LOUT+/- transmit signals are internally routed to the receiver input circuit. The incoming line receiver AMI signal on LIN+/- is ignored. With the transmitter still tied to the cable, this test mode can indicate a short circuit on the transmitter external components or other problem in the transmit path. REMOTE LOOP-BACK: When LPBK pin is allowed to float, the 78P7200L enters remote loopback mode. The RPOS/RNEG and RCLK pins are internally tied to the TPOS/TNEG and TCLK so the same AMI signal that is received by the framer is transmitted back to the far end where a bit continuity test can be performed. LINE BUILD-OUT: The Line Build-Out function controls the amplitude in DS3 and STS-1 mode. The selection of LBO depends on the amount of cable the transmitter is connected to. When used with less than 225 ft of cable the LBO pin should be pulled high. With 225ft or more cable the LBO pin should be low.
3
78P7200L E3/DS3/STS-1 Transceiver
PIN DESCRIPTION: THE 28-PIN PLCC IS COMPATIBLE WITH 78P7200 AND 78P2241 NAME LIN+ LINRCLK RPOS/ RNRZ RNEG LOS PIN TQFP 42 44 33 35 34 39 PIN PLCC 1 3 23 25 24 27 TYPE I O O O O DESCRIPTION Line Input: Differential AMI inputs to the chip. Should be transformer coupled and terminated at 75-ohm resistor. Receive Clock: Recovered receive clock. Receive Positive Data / NRZ Data: This pin indicates reception of a positive AMI pulse on the coax cable. Receive Negative Data: This pin indicates reception of a negative AMI pulse on the coax. Loss of Signal: logic low indicates that receiver signal (LIN) is below the threshold level RPOS and RNEG are forced low when LOS=0. Line Out: Differential AMI Output. Requires a 2:1 center tapped transformer and 301 resistor. Transmitter Clock Input: This signal is used to latch the TPOS/TNRZ and TNEG signals into the 78P7200L. Transmit Positive Data / Transmit NRZ: A logic one on this pin generates a positive AMI pulse on the coax. This pin should not be high at the same time that TNEG is high. Transmit Negative Data: A logic one on this pin generates a negative AMI pulse on the coax. This pin should not be high at the same time that TPOS/TNRZ is high. Line Build-Out, Transmitter: Logic low used with 225ft or more of cable is used on transmit path. Logic high used with less than 225ft of cable. DS3, E3 and STS-1 Select: Set low for E# applications. Set high for DS3, allow to float for STS-1 operation. Formerly OPT! on the 78P7200. Transmitter Enable: When high, enables transmitter. When low, tri-states transmitter drivers, LOUT. This pin was called OPT@ on 78P7200. Invert Clock Polarity: When low, the polarities of RCLK and TCLK are the same as those on the 78P7200. When set high, the polarity of TCLK is inverted. When allowed to float, the polarities of both RCLK and TCLK are inverted. Loop-back Select: When high, neither loop-back is activated. When allowed to float RPOS, RNEG and RCLK are looped back onto TPOS, TNEG and TCLK. When low, LOUT is looped back onto LIN. Power Supply. No Connect
LOUT+ LOUTTCLK TPOS/ TNRZ
9 11 18 16
9 11 16 14
O I I
TNEG
17
15
I
LBO
13
12
I
E#
15
13
I3
TXEN
22
18
I
ICKP
10
10
I3
LPBK
40
28
I3
VCC N/C
5,6,20, 21,37,38 27, 28
7,17,26 20, 21
P
4
78P7200L E3/DS3/STS-1 Transceiver
PIN DESCRIPTION: THE 28-PIN PLCC IS COMPATIBLE WITH 78P7200 AND 78P2241(continued) NAME GND PIN TQFP 1, 3, 4, 7, 8, 12, 14, 19, 23, 24, 25, 29, 30, 31, 32, 36, 41, 43, 45, 46, 47, 48 2 PIN PLCC 2, 4, 6, 8, 22 TYPE P DESCRIPTION Ground. Connecting all ground pins to a common ground plane is recommended.
RFO
5
-
LF1
26
19
-
A resistor to GND sets the operational speed of the chip. RFO= 5.23K for DS3, RFO=6.81K for E3 and RFO=4.53K for STS-1. Receiver PLL filter capacitor.
Note 1: Pin type: I-input; I3-three level logic input; O-output; P-power supply. Advanced Data sheet pin assignment and functions are subject to change.
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78P7200L E3/DS3/STS-1 Transceiver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS Operation beyond these maximums rating may permanently damage the device. PARAMETER Positive supply, VCC Storage temperature Ambient operating temperature Output Pin Voltage (LOUT+, LOUT-) Input Pin Voltage (LIN+, LIN-) Input pin voltage, all other pins VCC+0.3 to GND-0.3 V RATING 6V -65 to 150 -40 to +85 C VCC -2 to VCC +2 V
DC CHARACTERISTICS: Ta = -40 to +85C; positive supply voltage = 5V 0.5V or 3.3V0.3V PARAMETER Supply current ICC Supply current ICC VIL VIH IIL, IIH VIL3 ZIM3 VIH3 IIL3, IIH3 VOL VOH I I I I3 I3 I3 I3 O O IOL=-0.1mA IOL=+0.1mA VCC-0.5 Input Floating 8 VCC-0.5 -100 +100 0.5 10 2.0 -10 +10 0.5 20 PIN TYPE CONDITION Transmit and receive all ones, VCC=5V or 3.3V transmitter disabled, TXEN=0 MIN TYP 70 35 0.8 MAX 95 UNIT mA mA V V uA V k V uA V V
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78P7200L E3/DS3/STS-1 Transceiver
E3 - receiver (RFO = 6.81k , E# is set low), receiver is transformer-coupled. PARAMETER Peak Differential Input Amplitude, LIN+, LINBit Error Ratio in the presence of an Interfering Signal at Receive Input RCLK rise/fall time TRCT RCLK period, TRCF RCLK clock duty cycle RCLK pulse width TRC RPOS/RNEG data setup time TRDPS RPOS/RNEG data hold time TRDPH CL=15 pF CL=15 pF 7 7 45 14.55 CONDITION See Note 2 Interfering signal power 20dB below E3 signal power. Both are PRBS23 23 (2 -1) patterns. 2 29.10 55 MIN 104 10
-9
TYP
MAX 1200
UNIT mVpk
4
ns ns % ns ns
Note 2: 104 mVpk equals 950 mVpk at the source with 1100 feet of cable (13.2dB loss).
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78P7200L E3/DS3/STS-1 Transceiver
DS3/STS-1 RECEIVER (RFO = 5.23K FOR DS3 AND 4.53K FOR STS-1, E# PIN IS SET HIGH OR ALLOWED TO FLOAT), INPUT IS TRANSFORMER COUPLED PARAMETER Peak Differential Input Amplitude, LIN+ and LIN(see Note 3) Peak Differential Input Amplitude, LIN+ and LINBit Error Ratio in the presence of an Interfering Signal (IS) at LIN+,LINRCLK rise/fall time TRCT RCLK period TRCF RCLK pulse width TRC RPOS/RNEG data setup time TRDPS RPOS/RNEG data hold time TRPDH CONDITION Signal at DSX is 360-850mVP (see Note 4) DS3 HIGH (see Note 5) MIN 90 TYP MAX 850 UNIT mVP
90
1200
mVP
IS is a sinusoidal tone, 22.368 MHz for DS3 or 25.92MHz for STS-1. Data 15 is a PRBS15 (2 -1) pattern. IS power is 10dB below data signal power. Cl=25pf DS3 STS-1 DS3 STS-1 CL=15 pF CL=15 pF
10-9
5 22.35 19.29 12.24 9.65 7 7
ns ns ns ns ns
Note 3: Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSIT102.1993 Figure 5, Loss characteristics of the WE728A or RG 59B cable should be better than Figure C2 of ANSI-T102.1993. Note 4: Receiver can handle up to 450 feet of cable loss (5.5dB) from the DSX cross-connect. Note 5: Case where test signal is fed directly into receiver with fast rise times violates DS3 template and normal maximum. Interfering signal performance is not guaranteed in the presence of DS3 High at the input..
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78P7200L E3/DS3/STS-1 Transceiver
TIMING DIAGRAM: RECEIVE WAVEFORMS (E3/DS3/STS-1)
RECEIVE LINE INPUT (REF) LIN+/LINTRCF TRC RCLK ICKP=LOW or HIGH RCLK ICKP=FLOAT TRCT TRCT
TRDPS
TRDPH
RPOS TRDNS TRDNH
RNEG
TRDN
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78P7200L E3/DS3/STS-1 Transceiver
RECEIVER JITTER TOLERANCE E3 and DS3 jitter tolerance specifications are in ITU-T G.823 and G.824. The test condition can be found in ITU-T O.171. The E3 specification is the tighter of the two for frequencies greater than 20 kHz. Receive jitter tolerance is not tested during production test.
100
10 E3 DS3
1
0.1
0.01 1.E-05
1.E-03
1.E-01
1.E+01 1.E+03
1.E+05
1.E+07
PARAMETER Receiver Jitter Tolerance
CONDITION 12Hz to 2.78 Hz 10Hz to 600Hz 20 kHz to 800 kHz 5
MIN 18 0.15
NOM
MAX
UNIT UI
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78P7200L E3/DS3/STS-1 Transceiver
RECEIVER JITTER TRANSFER FUNCTION The receiver clock recovery loop filter characteristics are such that the receiver has the following transfer function. The corner frequency of the PLL is approximately 50 kHz. Receiver jitter transfer function is not tested during production test.
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
PARAMETER Receiver Jitter transfer function Jitter transfer function roll-off
CONDITION below 59.6 kHz
MIN
NOM 20
MAX 0.1
UNIT dB dB per decade
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78P7200L E3/DS3/STS-1 Transceiver
E3 - TRANSMITTER (RFO = 6.81K , E# = LOW) PARAMETER Transmitter amplitude Transmitter Amplitude Mismatch CONDITION (SEE TIMING DIAGRAM) LOUT+ and LOUTRatio of amplitudes of positive and negative pulses measured at pulse centers Ratio of widths of positive and negative pulses measured at pulse half amplitude LOUT+ and LOUT40 TTCF 0.8 2.5 2.5 29.10 14.55 3 5 MIN 950 0.95 TYP 1000 MAX 1050 1.05 UNIT mVP
Transmitter width mismatch TTPL/TTHL Transmitter Pulse width TTPL, TTPN Transmitter clock duty cycle, TTC/TTCF Transmitter clock period Transmitter clock pulse width , TTC Transmitter clock transition time, Rising and falling CPTT/CNTT Data setup time Data hold time TTDRS TTDHS
0.95
1.05
14.55 60
ns % ns ns ns ns ns
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78P7200L E3/DS3/STS-1 Transceiver
DS3/STS-1 TRANSMITTER (E # = High) PARAMETER Transmitter Amplitude Transmitter Amplitude Mismatch CONDITION LOUT+ and LOUTRatio of amplitudes of positive and negative pulses measured at pulse peaks. DS3 only - All ones, 3kHz bandwidth DS3 only - All ones, 3kHz bandwidth MIN 750 0.9 TYP 800 MAX 850 1.1 UNIT mVP
Transmitter power At 22.368 MHz Transmitter power At 44.736 MHz Transmitter clock duty cycle, TTC/TTCF Transmitter clock period Transmitter clock period Data setup time Data hold time TTCF TTCF TTPDS TTPDH
-1.8 -21.8 40
+5.7 -14.3 60 22.35 19.29
dBm dBm % ns ns ns ns
DS3 STS-1 2.5 2.5 0.8
Transmitter clock transition time, Rising and falling TTCPT,TTCNT
2
4
ns
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78P7200L E3/DS3/STS-1 Transceiver
TIMINGING DIAGRAM: TRANSMITTER WAVEFORMS (E3/DS3/STS-1)
TCLK ICKP=HIGH or FLOAT
TTCF TTC
TTCPT
TTCNT
TCLK ICKP=LO W TTPDS TTPDH
TPOS
TTNDS
TTNDH
TTPL VP 0.5 VP
0.5 VN VN TTNL
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78P7200L E3/DS3/STS-1 Transceiver
E3 TRANSMIT TEMPLATE
17 ns
0.2 0.1 1.0 0.1 0.2 8.65 ns
14.55 ns
0.5
12.1 ns
0.1 0 0.1 0.2
24.5 ns
0.1 0.1
29.1 ns
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78P7200L E3/DS3/STS-1 Transceiver
DS3 TRANSMIT PULSE TEMPLATE
1.2
1
0.8 Normalized Amplitude
0.6
0.4
0.2
0
-0.2 -1 -0.5 0 Time, Unit Intervals 0.5 1 1.5
TIME AXIS RANGE (UI) UPPER CURVE -0.85 < T < -0.68 -0.68 < T < 0.36 0.36 < T < 1.4 LOWER CURVE -0.85 < T < -0.36 -.0.36 < T < 0.36 0.36 < T < 1.4
NORMALIZED AMPLITUDE EQUATION 0.03 0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]} 0.08+0.407 e-1.84(T-0.36) -0.03 -0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]} -0.03
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78P7200L E3/DS3/STS-1 Transceiver
STS-1 TRANSMIT PULSE TEMPLATE
1.2
1
0.8
Normalized Amplitude
0.6
0.4
0.2
0
-0.2 -1 -0.5 0 Time, Unit Intervals 0.5 1 1.5
STS-1 (Transmit template specs) TIME AXIS RANGE (T) UPPER CURVE -0.85 < T < -0.68 -0.68 < T < 0.26 0.26 < T < 1.4 LOWER CURVE -0.85 < T < -0.38 -0.38 < T < 0.36 0.36 < T < 1.4 -0.03 -0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]} -0.03 0.03 0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]} 0.1+0.61 e-2.4(T-0.26) NORMALIZED AMPLITUDE EQUATION (A)
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78P7200L E3/DS3/STS-1 Transceiver
TRANSMITTER OUTPUT JITTER The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, and ANSI T1.102-1993 for all supported rates. Transmit output jitter is not tested during production test.
Jitter Detector Transmitter Output
20dB/decade
Measured Jitter Amplitude
10Hz
800kHz
PARAMETER Transmitter Output Jitter
CONDITION 10 Hz to 800 kHz
MIN
NOM
MAX 0.1
UNIT UI
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78P7200L E3/DS3/STS-1 Transceiver
E3/DS3/STS-1 EXAMPLE CIRCUIT
VCC
F1 FERRITE BEAD VCC 0.1uF J1 BNC 1 TR 75 2 3 4 RFO 5 RFO LIN+ GND 26 LINGND RPOS/RNRZ RNEG RCLK 25 24 23 FRAMER/ DEFRAMER 7 FERRITE BEAD 0.001uF J2 BNC TT VCC 301 1:2ct 11 10 LBO SPEED SELECT VCC 18 12 13 CLF LF1 ICKP(NCT) LBO E# (OPT!) TXEN ( OPT@) TCLK TNEG TPOS/TNRZ GND GND GND 16 15 14 19 9 LOUT+ 0.1uF 78P2241 VCC 0.1uF VCC 0.001uF 17 U1 10K 28 27 LOOP BACK SELECT
VCC LPBK(CPD) LOS (LOWSIG)
F2 VCC
LOUT-
0.047uF RT
Note 6: Pin names in ( ) denote pin names from 78P7200. Pin numbers refer to 28 PLCC package. Default settings used to simulate 78P7200. Note 7: Resistors on TCLK, TNEG, TPOS are optional but recommended. Clock pulse shapes at the inputs to the 78P7200L are dependent on board layout and will dictate the need for such added resistors. Note 8. Adding a series Ferrite Bead on VCC pins may be required for some pc board layout. EXTERNAL COMPONENTS (COMMON TO E3/DS3/STS-1) COMPONENT Receiver Termination Resistor Receiver Transformer Turns Ratio Transmitter Termination Resistor Transmitter Transformer Turns Ratio RTR TR RTT TT TOLERANCE 1% 3% 1% 3% VALUE 75 1:1 301 1:2ct UNIT -- ---
EXTERNAL COMPONENTS (DEPENDANT ON SPEED, NOMINAL VALUE) COMPONENT Loop Filter Capacitor Bias Resistor CLF RFO TOLERANCE 10% 1% STS-1 0.047 4.53 DS3 0.047 5.23 E3 0.047 6.81 UNIT F k
Note 9: Advanced Data sheet pin assignment, functions and external component values are subject to change.
6 22
8
19
78P7200L E3/DS3/STS-1 Transceiver
78P7200L REPLACEMENT FOR EXISTING 78P7200 DESIGNS
VCC LVCC
RVCC J1 BNC T1 R1 L2 C2 R2 RTR 2 3 C3 4 RFO 5 RVCC VCC LVCC 7 VCC 78P2241 J2 BNC TT VCC CTT RTT RLF1 1:2ct 11 10 LBO OPT1 OPT2 12 13 18 LOUTLF1 ICKP(NCT) LBO E3(OPT!) GND GND TXEN(OPT@) TCLK TNEG TPOS/TNRZ GND 16 15 14 19 CLF RT TCLK TNEG TPOS 9 LOUT+ RLF2 RVCC RFO GND RPOS/RNRZ RNEG RCLK 25 24 23 RPOS RNEG RCLK GND LVCC LINVCC 26 VCC 1 LIN+ C1 L1 U1
17 VCC CPD LPBK (CPD) LOS(LOWSIG) 28 27 LOW_SIG
COMPONENT VARIATION FOR EXISTING 78P7200 DESIGNS COMPONENT INPUT FILTER R1,R2 C2 L2 L1 C1 C3 T1 RTR CPD PLL FILTER RLF2 RLF1 TRANSMITTER CLF1 RTT CTT POWER SUPPLY LVCC 78P7200 75 82p 6.8u 0.47u 1000p 0.01 1:2 422 0.22u 100k 6.04k 0.22u DS3 E3 DS3 E3 4.7uH 78P7200L SHORT (0) NOT INSTALLED NOT INSTALLED NOT INSTALLED NOT INSTALLED NOT INSTALLED 1:1 75 SHORT (0) NOT INSTALLED NOT INSTALLED 0.047u 301 604 5-15pF 3pF 301 301 NOT INSTALLED NOT INSTALLED SHORT (0) or Ferrite Bead
20
6 22
8
78P7200L E3/DS3/STS-1 Transceiver
PACKAGE PIN DESIGNATIONS (Top View)
CAUTION: Use handling procedures necessary for a static sensitive component.
LPBK
GND
GND
4 RFO GND VCC GND LOUT+ ICKP LOUT5 6 7 8 9 10 11
3
2
1
28 27 26 25 24 23 22 21 20 19 RPOS RNEG RCLK GND N/C N/C LF1
12 13 14 15 16 17 18
RNAZ VCC LBO E# TNEG TXEN TCLK
28-Pin PLCC
(Not drop-in compatible to 78P7200)
21
VCC
LIN+
LOS
LIN-
78P7200L E3/DS3/STS-1 Transceiver
PACKAGE PIN DESIGNATIONS (Top View)
CAUTION: Use handling procedures necessary for a static sensitive component.
GND LPBK
GND
GND
GND
GND
GND
LIN+
VCC 38
48
47
46
45
44
43
42
41 40
39
GND RFO GND GND VCC VCC GND GND LOUT+ ICKP LOUTGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
37 36 35 34 33 32 31 30 29 28 27 26 25 24
VCC
LOS
LIN-
GND RPOS RNEG RCLK GND GND GND GND N/C N/C LF1 GND
VCC
GND
VCC
LBO
GND
TPOS
TNEG
TCLK
48-PIN TQFP
(Not drop-in compatible to 78P7200)
22
TXEN
GND
GND
E#
78P7200L E3/DS3/STS-1 Transceiver
MECHANICAL DRAWING 28-Pin PLCC
23
78P7200L E3/DS3/STS-1 Transceiver
MECHANICAL DRAWING 48-Pin TQFP
ORDERING INFORMATION PART DESCRIPTION 28-pin PLCC 48-pin TQFP ORDER NUMBER 78P7200L-IH 78P7200L-IGT PACKAGE MARK 78P7200L-IH 78P7200L-IGT
Advanced Information: Indicates a product is either in prototype testing or undergoing design evaluation prior to full production release. Specifications are based on design goals or preliminary evaluation and are not guaranteed. Small quantities are usually available and TDK Semiconductor Corporation should be consulted for current information. No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877 (c)2000 TDK Semiconductor Corporation 06/06/00 - rev . B
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